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2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC)

2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC)

17th Asia and South Pacific Design Automation Conference

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

2009 Asia and South Pacific Design Automation Conference

2008 Asia and South Pacific Design Automation Conference

2007 Asia and South Pacific Design Automation Conference

Asia and South Pacific Conference on Design Automation, 2006.

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005.

Volume 2 - 2005

Volume 1 - 2005

Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference 2005 (IEEE Cat. No.05EX950C)

Proceedings of the ASP-DAC 2005 Asia and South Pacific Design Automation Conference 2005

ASP-DAC 2005 General Chair's Message

Technical Program Co-Chairs' message

University LSI Design Contest

The development of integrated circuit industry in China [Keynote Address I]

Silicon compilation: the answer to reducing IC development costs [Keynote Address II]

Design at the end of the silicon roadmap

ASP-DAC 2005 Best Papers

ASP-DAC Steering Committee

ASP-DAC 2005 Technical Program Committee

University LSI Design Contest Committee

List of reviewers

Table of contents

Design at the end of the silicon roadmap [Keynote Address III]

Who is responsible for the design for manufacturability issues in the era of nano-technologies? [Panel I]

Are we ready for system-level synthesis? [Panel II]

EDA market in China [Panel III]

Challenges to covering the high-level to silicon gap

Opportunities and challenges for better than worst-case design

Microarchitecture evaluation with floorplanning and interconnect pipelining

Design for manufacturability

Leakage power: trends, analysis and avoidance

Designing reliable circuit in the presence of soft errors

The polygonal contraction heuristic for rectilinear Steiner tree construction

An-OARSMan: obstacle-avoiding routing tree construction with good length performance

Making fast buffer insertion even faster via approximation techniques

Concurrent flip-flop and buffer insertion with adaptive blockage avoidance

Buffering global interconnects in structured ASIC design

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees

Time and energy efficient mapping of embedded applications onto NoCs

Communication-driven task binding for multiprocessor with latency insensitive network-on-chip

System-level communication modeling for network-on-chip synthesis

MAIA - a framework for networks on chip generation and verification

Theoretic analysis and enhanced x-tolerance of test response compact based on convolutional code

Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation

Testing comparison faults of ternary CAMs based on comparison faults of binary CAMs

SPIN-PAC: test compaction for speed-independent circuits

A Huffman-based coding with efficient test application

ESDZapper: a new layout-level verification tool for finding critical discharging path under ESD stress

A new method for model based frugal OPC

Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up

Analysis of buffered hybrid structured clock networks

Clock network minimization methodology based on incremental placement

A multi-level transmission line network approach for multi-giga hertz clock distribution

Gibbs sampling in power grid analysis

A wideband hierarchical circuit reduction for massively coupled interconnects

A min-area solution to performance and RLC crosstalk driven global routing problem

Thermal-driven multilevel routing for 3D ICs

Wave-pipelined on-chip global interconnect

Evaluation of on-chip transmission line interconnect using wire length distribution

A formalism for functionality preserving system level transformations

Embedded software generation from system level specification for multi-tasking embedded systems

Scheduler implementation in MP SoC design

Optimizing embedded applications using programmer-inserted hints

Static analysis and automatic code synthesis of flexible FSM model

Constraint extraction for pseudo-functional scan-based delay testing

Bridging fault detection in double fixed-polarity Reed-Muller (DFPRM) PLA

Propagation delay fault: a new fault model to test delay faults

Oscillation ring based interconnect test scheme for SoC

Bridging fault testability of BDD circuits

Yield driven gate sizing for coupling-noise reduction under uncertainty

Maze routing with OPC consideration

Towards automatic parameter extraction for surface-potential-based MOSFET models with the genetic algorithm

Substrate resistance extraction with direct boundary element method

An efficient combinationality check technique for the synthesis of cyclic combinational circuits

Library cell layout with Alt-PSM compliance and composability

Forward discrete probability propagation method for device performance characterization under process variations

Wideband modeling of RF/analog circuits via hierarchical multi-point model order reduction

Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams

A new approach for ring oscillator simulation using the harmonic balance method

Efficient transient simulation for transistor-level analysis

Block SAPOR: block second-order Arnoldi method for passive order reduction of multi-input multi-output RCS interconnect circuits

Block based statistical timing analysis with extended canonical timing model

FSM re-engineering and its application in low power state encoding

Post-layout logic duplication for synthesis of Domino circuits with complex gates

Detecting support-reducing bound sets using two-cofactor symmetries

Synthesis of quantum logic circuits

STACCATO: disjoint support decompositions from BDDs through symbolic kernels

A framework for automated and optimized ASIP implementation supporting multiple hardware description languages

A processor core synthesis system in IP-based SoC design

Speed and voltage selection for GALS systems based on voltage/frequency islands

A system-level approach to hardware reconfigurable systems

High-level synthesis for DSP applications using heterogeneous functional units

Evaluation of the statistical delay quality model

Fault tolerant nanoelectronic processor architectures

An efficient control-oriented coverage metric

An observability measure to enhance statement coverage metric for proper evaluation of verification completeness

Tightly integrate dynamic verification with formal verification: a GSTE based approach

On structure and suboptimality in placement

Optimal placement by branch-and-price

Detailed placement for improved depth of focus and CD control

Floorplan management: incremental placement for gate sizing and buffer insertion

Low-power techniques for network security processors

A configurable AES processor for enhanced security

Power estimation strategies for a low-power security processor

Design and test of a scalable security processor

System-level design space exploration for security processor prototyping in analytical approaches

Fast and effective gate-sizing with multiple-V/sub t/ assignment using generalized Lagrangian relaxation

Effective analytical delay model for transistor sizing

Achieving continuous V/sub T/ performance in a dual V/sub T/ process

Runtime leakage minimization through probability-aware dual-V/sub t/ or dual-T/sub ox/ assignment

Floorplanning for 3-D VLSI design

Optimal redistribution of white space for wire length minimization

Crowdedness-balanced multilevel partitioning for uniform resource utilization

Partitioning and placement for buildable QCA circuits

PMP: performance-driven multilevel partitioning by aggregating the preferred signal directions of I/O conduits

MUP: a minimal unsatisfiability prover

Integration of supercubing and learning in a SAT solver

Dynamic symmetry-breaking for improved Boolean optimization

A fast counterexample minimization approach with refutation analysis and incremental SAT

Sequential equivalence checking using cuts

Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop nonidealities and supply noise

Hierarchical analysis of process variation for mixed-signal systems

A novel wavelet method for noise analysis of nonlinear circuits

An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels

Partial reluctance based circuit simulation is efficient and stable

SAGA: synthesis technique for guaranteed throughput NoC architectures

Automated throughput-driven synthesis of bus-based communication architectures

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks

Statistical modeling of cross-coupling effects in VLSI interconnects

Compact and stable modeling of partial inductance and reluctance matrices

Scalable interprocedural register allocation for high level synthesis

Simultaneous floorplanning and resource binding: a probabilistic approach

Reducing hardware complexity of linear DSP systems by iteratively eliminating two-term common subexpressions

A fast algorithm for finding common multiple-vertex dominators in circuit graphs

Low-power domino circuits using NMOS pull-up on off-critical paths

Low-leakage robust SRAM cell design for sub-100nm technologies

Studying interactions between prefetching and cache line turnoff

The development of high performance FFT IP cores through hybrid low power algorithmic methodology

A variation-aware low-power coding methodology for tightly coupled buses

Automatic assume guarantee analysis for assertion-based formal verification

TED+: a data structure for microprocessor verification

Improved Boolean function hashing based on multiple-vertex dominators

Lower bounds for dynamic BDD reordering

Partitioned model checking from software specifications

Register placement for low power clock network

Skew scheduling and clock routing for improved tolerance to process variations

Stability analysis of active clock deskewing systems using a control theoretic approach

Process variation robust clock tree routing

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing

An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC

A new register file access architecture for software pipelining in VLIW processors

A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264

Automatic synthesis and scheduling of multirate DSP algorithms

A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction

Exploiting temporal idleness to reduce leakage power in programmable architectures

Methodology for high level estimation of FPGA power consumption

Leakage control in FPGA routing fabric

Call for papers ASP-DAC 2006

Battery aware instruction generation for embedded processors

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design

Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)

Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106)

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

Proceedings of 1998 Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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