NDLI: Novel High Speed Robust Latch

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2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Table of Contents

Message from the Symposium Chairs

Program Committee

In Memoriam: Professor Susumu Horiguchi

TTTC: Test Technology Technical Council

The Future of Test -- Product Integration and its Impact on Test

Low DPM: Why Do We Need it and What Does it Cost!

Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems

Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points

Soft Core Embedded Processor Based Built-In Self-Test of FPGAs

On-chip Generation of the Second Primary Input Vectors of Broadside Tests

Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience

A Novel Hardened Design of a CMOS Memory Cell at 32nm

Novel High Speed Robust Latch

Are Robust Circuits Really Robust?

Challenges in Delay Testing of Integrated Circuits

Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories

Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power

Coded DNA Self-Assembly for Error Detection/Location

Errors in DNA Self-Assembly by Synthesized Tile Sets

Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs

Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors

SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000

Reduced Precision Checking for a Floating Point Adder

Characterization of Gain Enhanced In-Field Defects in Digital Imagers

Analysis of Resistive Open Defects in a Synchronizer

A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems

On the Functional Qualification of a Platform Model

A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits

A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance

Improving Memory Repair by Selective Row Partitioning

Software-Based Hardware Fault Tolerance for Many-Core Architectures

Can Functional Test Achieve Low-cost Full Coverage of NoC Faults?

Testing of Switch Blocks in Three-Dimensional FPGA

A Study of Side-Channel Effects in Reliability-Enhancing Techniques

Reliability and Performance Analysis of FPGA-Based Fault Tolerant System

An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs

Minimizing Observation Points for Fault Location

Optimizing Parametric BIST Using Bio-inspired Computing Algorithms

Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms

System Level Testing via TLM 2.0 Debug Transport Interface

Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments

Transient Error Detection and Recovery in Processor Pipelines

Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels

Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis

Complementary Formal Approaches for Dependability Analysis

Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR)

An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level

Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences

Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes

Resilience Challenges for Exascale Systems

Improving the Detectability of Resistive Open Faults in Scan Cells

An Incremental Approach to Functional Diagnosis

Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning

Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip

Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors

A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS

Error Correction Codes for SEU and SEFI Tolerant Memory Systems

Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip

Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects

Data Learning Techniques for Functional/System Fmax Prediction

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

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03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in