NDLI: Detection of an antenna effect in VLSI designs

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2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems

2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems

22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007)

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings.

Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems

17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings.

Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99)

Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223)

1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

International Symposium on Defect and Fault Tolerance in VLSI Systems

Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Making defect avoidance nearly invisible to the user in wafer scale field programmable gate arrays

Extraction of critical areas for opens in large VLSI circuits

Fault probability prediction for array based designs

Yield prediction by sampling with the EYES tool

Application of a survey sampling critical area computation tool in a manufacturing environment [IC yield]

Yield-performance tradeoffs for VLSI processors with partially good two-level on-chip caches

Integration of DFM techniques and design automation

Trade-offs between yield and reliability enhancement [VLSI]

Layer reassignment for antenna effect minimization in 3-layer channel routing

Detection of an antenna effect in VLSI designs

Integrated approach for circuit and fault extraction of VLSI circuits

Layout-driven detection of bridge faults in interconnects

Test sequence generation for realistic faults in CMOS ICs based on standard cell library

Impact of physical defects on the electrical working of embedded DRAM with 0.35 /spl mu/m design rules

A statistical parametric and probe yield analysis methodology [IC manufacture]

The prediction of circuit performance variations for deep submicron CMOS processes

Maximum likelihood estimation for yield analysis [IC manufacture]

Comprehensive modeling of VLSI test

Modeling quality reduction of multichip module systems due to uneven fault-coverage and imperfect diagnosis

Error identification and data retrieval in signature analysis based data compaction

Experimental results from I/sub DDF/ testing

A unified approach for off-line and on-line testing of VLSI systems

Compact and highly testable error indicator for self-checking circuits

Tree checkers for applications with low power-delay requirements

A parametric design of a built-in self-test FIFO embedded memory

Fault-tolerant shuffle-exchange and de Bruijn networks capable of quick broadcasting

Fault tolerant Newton-Raphson dividers using time shared TMR

Balancing of fault tolerance in the new version of the FERMI Channel chip: a functional evaluation

Fault detection and fault tolerance issues at CMOS level through AUED encoding

Optimising high-level synthesis for self-checking arithmetic circuits

Redundant faults in TSC networks: definition and removal

Reliable logic circuits with byte error control codes-a feasibility study

Configurable spare processors: a new approach to system level fault-tolerance

ROM-based synthesis of fault-tolerant controllers

Implementing fault injection and tolerance mechanisms in multiprocessor systems

Recovery schemes for mesh arrays utilizing dedicated spares

KITE: a behavioural approach to fault-tolerance in FPGA-based systems

Reconfiguration of 1 1/2 track-switch mesh-arrays with PE and bus faults

Index of authors

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in