NDLI: PEAS-III: an ASIP design environment

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PEAS-III: an ASIP design environment

Content Provider	IEEE Xplore Digital Library
Author	Itoh, M. Higaki, S. Sato, J. Shiomi, A. Takeuchi, Y. Kitajima, A. Imai, M.
Copyright Year	2000
Description	Author affiliation: Osaka Univ., Japan (Itoh, M.)
Abstract	In this paper, an architectural level processor design environment PEAS-III is proposed. Pipelined processors designed by this system can include multi-cycle operation, delayed branch and external interrupt. The data path and control logic of the processor are generated from the clock based micro-operation description of instructions. The ease of large design space exploration through experiments using several subsets of MIPS R3000 instruction set.
Starting Page	430
Ending Page	436
File Size	799636
Page Count	7
File Format	PDF
ISBN	0769508014
ISSN	10636404
DOI	10.1109/ICCD.2000.878319
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-09-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific processors Pipelines Process design Logic Clocks Hardware Specification languages Timing Registers Educational institutions
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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