NDLI: Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits

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Synthesis and optimization procedures for robustly delay-fault testable combinational logic circuits

Content Provider	ACM Digital Library
Author	Devadas, Srinivas Keutzer, Kurt
Abstract	In this paper we apply recently developed necessary and sufficient conditions for robust path-delay-fault testability to develop synthesis procedures which produce two-level and multilevel circuits with high degrees of robust path delay fault testability. For circuits which can be flattened to two levels, we give a covering procedure which optimizes for robust path delay fault testability. These two-level circuits can then be algebraically factored to produce robustly path-delay-fault testable multilevel circuits. For regular structures which cannot be flattened to two levels, we give a composition procedure which allows for the construction of robustly path-delay-fault testable regular structures. Finally, we show how these two techniques can be combined to produce cascaded combinational logic blocks that are robustly path-delay-fault testable. We demonstrate these techniques on a variety of examples. It is possible to produce entire chips that are fully path delay testable using these techniques.
Starting Page	221
Ending Page	227
Page Count	7
File Format	PDF
ISBN	0897913639
DOI	10.1145/123186.123262
Language	English
Publisher	Association for Computing Machinery (ACM)
Publisher Date	1991-01-03
Publisher Place	New York
Access Restriction	Subscribed
Content Type	Text
Resource Type	Article

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